1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to a dual panel-type OELD device and a method of fabricating a dual panel-type OELD device.
2. Discussion of the Related Art
Presently, OELD devices are self-luminescent and do not require additional light sources. In addition, OELD devices have wide viewing angles and high contrast ratios, and are relatively small and lightweight, as compared to a liquid crystal display (LCD) devices and plasma display panel (PDP) devices. Moreover, OELD devices have low power consumption, and are commonly driven by low direct current (DC) voltages, thereby providing relatively short response times. Since OELD devices are solid state, they can operate within a wide range of temperatures, and are unlikely to be damaged by external impacts. Furthermore, as compared to LCD devices or PDP devices, OELD devices have reduced manufacturing costs, wherein only deposition and encapsulation apparatuses are used for fabrication.
FIG. 1 is a cross sectional view of an OELD device according to the related art. In FIG. 1, an OELD device includes a first substrate 10 and a second substrate 60 facing the first substrate with a predetermined space therebetween. An array element layer AL is formed on an inner surface of the first substrate 10, and includes a thin film transistor T formed at each pixel region P, which is a minimum unit for an image. In addition, an organic electroluminescent diode E is formed on the array element layer AL. The organic electroluminescent diode E includes a first electrode 48, an organic light-emitting layer 54 and a second electrode 56 sequentially formed on the array element layer AL. Accordingly, light emitted from the organic light-emitting layer 54 is transmitted toward a transparent electrode of the first and second electrodes 48 and 56.
In general, OELD devices are categorized into one of two different types depending on an emission direction: top emission mode and bottom emission mode. In FIG. 1, the OELD device is a bottom emission mode type of OELD device, wherein the first electrode 48 is formed of a transparent material and the light emitted from the organic light-emitting layer 54 is transmitted through the first electrode 48.
In FIG. 1, the second substrate 60 serves as an encapsulation substrate, wherein a concavity 62 is formed at an inner surface of the second substrate 60 and a desiccant 64 is disposed within the concavity 62. The desiccant 64 removes any external moisture that may permeate into a space between the first and second substrates 10 and 60, thereby protecting the organic electroluminescent diode E. In addition, a seal pattern 70 is formed along peripheral portions of the first and second substrates 10 and 60, thereby sealing the first and second substrates 10 and 60.
FIG. 2A is a plan view of a pixel for an OELD device according to the related art, and FIG. 2B is a cross sectional view along II-II of FIG. 2B according to the related art. In FIGS. 2A and 2B, a buffer layer 12 is formed on a substrate 10, and a semiconductor layer 14 and a capacitor electrode 16 are formed on the buffer layer 10 with a space therebetween. Then, a gate insulating layer 18 and a gate electrode 20 are sequentially formed on a center portion of the semiconductor layer 14. The semiconductor layer 14 includes an active area 14a corresponding to the gate electrode 20, and source and drain areas 14b and 14c disposed at both sides of the active area 14a. In addition, a gate line 22 extending along a first direction is formed on the same layer as the gate electrode 20.
Next, a first passivation layer 24 covers the gate electrode 20 and the capacitor electrode 16. Then, a power electrode 26 is formed over the first passivation layer 24 corresponding to the capacitor electrode 16, wherein the power electrode 26 extends from a power supply line 28 that is formed to extend along a second direction crossing the first direction.
Then, a second passivation layer 30 is formed along an entire surface of the substrate 10 including the power electrode 26. The first and second passivation layers 24 and 30 include first and second contact holes 32 and 34 formed therethrough, wherein the first contact hole 32 exposes the drain area 14c of the semiconductor layer 14 and the second contact hole 34 exposes the source area 14b of the semiconductor layer 14. In addition, the second passivation layer 30 has a third contact hole 36 exposing a part of the power electrode 26.
Next, a source electrode 38 and a drain electrode 40 are formed on the second passivation layer 30, wherein the drain electrode 40 is connected to the drain area 14c of the semiconductor layer 14 through the first contact hole 32. In addition, the source electrode 38 is connected to the source area 14b of the semiconductor layer 14 through the second contact hole 34 and the power electrode 26 through the third contact hole 36.
In FIG. 2A, a data line 42 is formed on the same layer as the source and drain electrodes 38 and 40, and extending along the second direction to cross the gate line 22, thereby defining a pixel region P. Then, a third passivation layer 44 covers the drain electrode 40 and the source electrode 38, wherein the third passivation layer 44 has a drain contact hole 46 exposing a part of the drain electrode 40.
Next, a light-emitting area EA is defined on the third passivation layer 44, and a first electrode 48 is formed in the light-emitting area EA, wherein the first electrode 48 is connected to the drain electrode 40 through the drain contact hole 46. Then, an inter insulating layer 50 is formed on the first electrode 48 and the third passivation layer 44, thereby exposing the main portion of the first electrode 48 and covering edges of the first electrode 48. Subsequently, an organic light-emitting layer 54 is formed on the first electrode 48 and the inter insulating layer 50 within the light-emitting area EA, and a second electrode 56 is formed along an entire surface of the substrate 10 including the organic light-emitting layer 54.
In FIGS. 2A and 2B, the semiconductor layer 14, the gate electrode 20, the source electrode 38 and the drain electrode 40 constitute a driving thin film transistor Td, and is disposed between a switching thin film transistor Ts (in FIG. 2A) and the power supply line 28. The switching thin film transistor Ts is located at a crossing portion of the gate line 22 and the data line 42, and has the same structure as the driving thin film transistor Td.
In FIG. 2A, the gate electrode 20 of the driving thin film transistor Td is connected to the switching thin film transistor Ts, and the drain electrode 40 of the driving thin film transistor Td is formed having an island shape. Accordingly, the switching thin film transistor Ts includes another gate electrode that extends from the gate line 22 and another source electrode that extends from the data line 42. In addition, the power supply line 28 (including the power electrode 26) and the capacitor electrode 16 overlap each other to form a storage capacitor Cst.
Fabrication of the bottom emission mode OELD device includes attaching a substrate including array elements and organic luminescent diodes, and another substrate for encapsulation. Since fabrication yield of the OELD device is dependent upon fabrication yields of the array elements and the organic luminescent diodes, an entire fabrication yield is largely affected by fabrication of organic luminescent diode. Thus, even though the array elements may be properly fabricated, if the organic light-emitting layer is improperly fabricated, such forming the layer having a thickness of about 1,000 Å or incorporating impurities or other factors, the resulting OELD device will be determined to be unacceptable. Thus, all manufacturing costs and source materials required for fabrication of the array elements are wasted, and product yield is lowered.
Although the bottom emission mode OELD device has excellent stability and a certain degree of freedom in its fabrication processes, the bottom emission mode OELD device has a reduced aperture ratio. Thus, the bottom emission mode OELD device is not generally suitable for a high aperture device. Conversely, a top emission mode OELD device has a high aperture ratio, is easy to fabricate, and has a long operational lifetime. However, in the top emission mode OELD device, since a cathode is generally disposed over the organic light-emitting layer, a choice of material with which to make the cathode is limited. Accordingly, light transmittance is limited, and light-emitting efficacy is reduced. Furthermore, in order to improve the light transmittance, the passivation layer should be formed as a thin film, thereby preventing infiltration of the exterior moisture and air.